1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a ultra-high current drive MCS transistor suitable for use under a low supply voltage.
2. Description of the Prior Art
In the field of the MOS transistors, with the advance of the integration technique of the MOSFETs in particular, the device having a gate length within a range equal to or less than 0.5 xcexcm has been studied and developed at various places. In 1974, R. L. Dennard et al. have proposed the so-called scaling method for the MOSFET down-scaling. This method indicates that when the size of one composing element (e.g., channel length) of an element is required to be reduced, the operating characteristics of the transistor can be secured, as far as the other composing elements are reduced at the same reduction ratio. Basically, from the 1979a to the early 1990s, the higher integration technique of the MOSFETs has been realized on the basis of this scaling method.
With the advance of the higher and higher integration, however, various composing elements approach the respective limit values referred to as xe2x80x9climit valuesxe2x80x9d so that it has become difficult to further reduce the various composing elements beyond these limit values. For instance, since the limit of the thickness of the gate insulating film is generally considered as about 3 to 4 nm, when the film thickness is reduced below this value, direct tunneling current between the gate electrode and the source/drain electrode increases, so that it has been well known that the transistor cannot operate normally.
To overcome this problem, in 1993, Fiegna et al. have proposed such a technique that although the gate insulating film thickness is fixed to about 3 nm, the composing elements other than the gate insulating film can be reduced (as reported by Document (Writer): C. Fiegna, H. Iwai, T. Wada, T. Saito, E. Sangiorgio, and B. Ricco; (Title) a new scaling methodology for the 0.1 to 0.021 um MOSFET, xe2x80x98Dig. of Tech. Papers, VLSI Symp; (Source) Technol., Kyoto, pp. 33-34, 1993). On the basis of this technique, in the same year, Ono et al. have realized a translator having a gate length of 0.04 um, [as reported by Document (Writer): M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, and H. Iwai; (Title) Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junction: (Source) IEDM Tech. Dig., pp. 119 to 122, 1993).
The transistor having a gate insulating film thickness of 3 nm and a gate length of 0.04 nm was manufactured as follows: First, after an insulation region and been formed on a p-type silicon substrate in accordance with LOCOS (Local Oxidation of Silicon), p-type impurities (e.g., B (boron); were introduced into the channel forming region to such an extent that any required threshold voltage was obtained.
After that, as the gate oxide film, at oxide film of about 3 nm was formed on the surface of the silicon substrate by oxidation at 800Cxc2x0 for 10 min within a dry O2 atmosphere, for instance. Further, after poly silicon containing P (phosphorus) was deposited to a thickness of about 100 nm, a resist was applied, and the applied resist was patterned to obtain a gate electrode of a desired length. Further, n-type impurities were introduced into the source, drain forming region, by solid phase phosphorus diffusion from a PSG film (a silicon oxide film containing P (phosphorus)) remaining on the gate electrode side wall portion. After that, in order to improve the connection to the metal wiring portion and further to reduce the resistance of the diffusion layer portion (which exerts no influence upon the short channel effect of the transistor), n-type impurities (a dose: 5xc3x971015cmxe2x88x922) were introduced in accordance with the ion implantation method, for instance. At this time, the substrate was annealed at 1000C.xc2x0 for 10 min, for instance for impurity diffusion and motivation. After that, contact portions were opened, and metallization was formed.
In the transistor manufacture as described above, the sheet resistance (xcfx81s) of the source/drain diffusion layer under the gate side wall portion was 6.2 kxcexa9/xe2x96xa1, and the diffusion length (i.e., the depth of the source/drain region) was 10 nm, as a result of SIMS analysis.
In the above-mentioned prior art transistor, however, since the parasitic resistance increased relatively large due to the shallow source/drain region, it was impossible to obtain a high current drive capability corresponding to the reduction of the gate length.
With these problems in mind, therefore, it is the object of the present invention to provide a MCS type semiconductor device of high current drive capability.
According to the first aspect of the present invention, there is provided a semiconductor device, comprising:
a first-conductivity type semiconductor substrate;
an insulating film formed on said semiconductor substrate;
a gate electrode formed on said semiconductor substrate via said insulating film; and
a second-conductivity type source/drain region formed on both sides of a channel forming region located under said gate electrode formed on said semiconductor substrate via said insulating film; and
wherein a thickness of said insulating film is less than 2.5 nm at silicon oxide equivalent thickness; and a gate length of said gate electrode is equal to or less than 0.3 xcexcm.
According to the present invention, when the thickness of the gate insulating film is determined less than 2.5 nm, it is possible to improve the reliability of the device under the hot carrier stress as shown in FIG. 3. In addition, when the thickness of the gate insulating film is reduced 2 nm or less, the reliability can be further improved.
Further, as shown in FIG. 4, when the channel length is determined equal to or less than 0.3 xcexcm, the gate current can be reduced markedly, so that the transistor characteristics can be improved markedly.
Consequently, in the semiconductor device according to the present invention, when the gate length is determined equal to or less than 0.3 xcexcm and the gate insulating film thickness is determined less than 2.5 nm, a transistor of excellent operating characteristics and high hot carrier reliability can be realized.
According to the second aspect of the present invention, these is provided a semiconductor device, comprising:
a first-conductivity type semiconductor substrate;
an insulating film formed on said semiconductor substrate;
a gate electrode formed on said semiconductor substrate via said insulating film; and
a second-conductivity type source/drain region formed on both sides of a channel forming region located under said gate electrode formed on said semiconductor substrate via said insulating film; and
wherein a thickness of said insulating film is less than 2.5 nm at silicon oxide equivalent thickness; a gate length of said gate electrode is equal to or less than 0.3 xcexcm; and a voltage applied to said gate electrode and said drain region is determined to be 1.5 V or less.
According to the third aspect of the present invention, there is provided a semiconductor device, comprising:
a first-conductivity type semiconductor substrate;
an insulating film formed on said semiconductor substrate;
a gate electrode formed on said semiconductor substrate via said insulating film; and
a second-conductivity type source/drain region formed on both sides of a channel forming region located under said gate electrode formed on said semiconductor substrate via said insulating film; and
wherein a transconductance (gm) is as follows:
gm greater than 400 V33+140 in nMCS
gm greater than 160 VDD+10 in pMCS
where a unit of VDD is V and a unit of gm is mS/mm.
According to the fourth aspect of the present invention, there is provided a semiconductor device, comprising:
a MOS FET including:
a first-conductivity type semiconductor substrate;
an insulating film formed on said semiconductor substrate and having a thickness less than 2.5 nm at silicon oxide equivalent thickness film;
a gate electrode formed on said semiconductor substrate via said insulating film; and
a second-conductivity type source/drain region formed on both sides of a channel forming region located under said gate electrode formed on said semiconductor substrate via said insulating film; and
a Schottky diode formed of a metal/silicon layer having a breakdown voltage lower than that of said insulating film and connected to said gate electrode of said MOSFET.